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<br />;=��f ���ff,'� 4� ez��ineers has created the 1604 system for .
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<br />��rmaxxmum x��iab�l�ty Solid s�Cate coinponents are
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<br />fi� � us��,�i� throughour the ,160� ` and exrremel ' wide tol-
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<br />�''er�rices �:r�' d�s�gx�cd rnto all circuits :`
<br />r'�x ��sr c}y �`' 1 , t '
<br />;����, -y�ain���ance xs iaexlrtated by a�n unusually high
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<br />t;���d��xee` of standa�clyzation arid m�dul�rization
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<br />��thrc�tiighaut� the cqmputer All circuits are plu�gable..
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<br />,� y�`h� t U�sic b� 1�vel �amplifiei, invei ter's are;' direct�
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<br />i;a aavuplec�,, gtF pr�n�ed �irG� + con�tiruction, �rid oper
<br />�������'�,t a'ii�eq`u��al�nt�phas� `rate of five megac.yeles
<br />y 4�' �isa'+� ��� Y � pc � �" > . ? = '
<br />��p����con�l �'�'hr� cir��zit is r�pe�.ted 9000 t�mes in tl�.�
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<br />9�� P�i A��. � �i � ° s �` i ° ' �.
<br />�� �,+��aa��uker A total o�''�(�00 cards are used �n a single
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<br />��"16Q��"`�'��xc��ci�r�te�.y���00 `eards on �a�ch of the e�g�ht
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<br />�ia�netic Gore
<br />Stara�e Sect�on
<br />The storage section of the Model 1604 is a large-
<br />capacity magnetic core storage system providing
<br />high-speed, non-volatile, random-access storage
<br />for 32,768 48-bit words. 0„Q 48-bit word may
<br />contain either a 48-bit data word or two 24-bit
<br />instructions. The read access time, i.e., the time
<br />from request of data to delivery of data from stor-
<br />age, is 2.2 microseconds.
<br />The 32,768 48-bit word magnetic core storage
<br />section of the 1604 computer is controlled by a _
<br />two-phase timing system, each phase controlling
<br />one-half (16,384 — 48-bit words) of the total stor-
<br />age. All odd storage addresses reference one star-
<br />age unit, and all even addressEs reference the �
<br />other storage unit. The read access time of each
<br />section is 2.2 microseconds after which, without`, i
<br />delay, the next arithmetic operation is initiated. .
<br />Each unit has a total storage cycJe time of '''
<br />6.4 microseconds. The storage cycles of the two
<br />sections overlap one another in the execution of
<br />a program, with the result that the effective cycle '
<br />�,',
<br />time is 3.2 microseconds when addresses of al-
<br />ternate memory banks are referEnced. Average.' ,
<br />effective cycle time for random addresses is about ,;;
<br />4.8 microseconds for a representative program. �`'
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