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punched paper tape z�eader that reads 350 �char-
<br />acters per second; and the Teletype high-speed
<br />paper tape punch that operates at 60 characters
<br />per second. f�ptional input-Qutput equipment in-
<br />cludes an on-line electric typewriter, up to 8
<br />magnetic tape handlers (Ampex FR-300 handlers
<br />S Register (12 bits) : functions ; s the storage address
<br />register. Prior to any storage re►�rence, the address r`
<br />word is entered in S. 1'he contents oi S aze then
<br />used to setect the storage location involved in the
<br />reference.
<br />,- that operate at 30KC character rate or Ampex
<br />FR-400 handlers that operate at 15KC character � Register (6 bits): holds the upper six bits of .an
<br />rate), card reader-punch units, and line print�r. i�struction word, i.e., the function code, through=
<br />Input-output transmissions are either a single out the execution of an instruction. The e�ecution
<br />' of an instruction is under the control o� the
<br />fs �� , 6-bit or 7-bit character, or a 12-bit word.
<br />quantity in F.
<br />T
<br />4� _
<br />� >-
<br />''�°; 111--Description of Re isters IV—Addressin Mode�
<br />���,�� �� � _� g g �
<br />P Tn the direct addressin ' ( �
<br />The 160 Computer contains three o eratianal g mode d), the address refers
<br />� regiaters: A, Z, and P. The contents of these to a 12-bit operand in one of the first 64 storage � h y
<br />�, �`� registers are shawn in arabic numerals (octal locations. `+
<br />ti,
<br />z� ° notation) on the control panel of the computer.
<br />�' � There are also : three transient registers: B, F, Indirect addressin
<br />g(i) provides for opexand , r��er ;
<br />��r � `�nd S. These registers aze described below; a ences and jump addresses. Where indirect add�ress `. �,,;
<br />ti :
<br />„: block diagram of the 160 Computer is shown ing is used with an instructian, E refers ta one of '
<br />in Figure =1. � � �
<br />:,
<br />the first 64 storage locatians; the :contents of ; y' �
<br />this register are then read out and used , as the ; t-�
<br />A liegister. (1�� bits):; principal.arithmetic register. For ad�ress of the operan d or as the jump address �-
<br />F Y
<br />most�' aritt�metic ope� ations, A ogerates as a 12- '��$i
<br />,� .� bit subtractive accumulator The quantity zero Relative addressing;provides for operand addressos .� �'�,�
<br />JSy�
<br />� is represented by all zeros. and jump addresses that are in the immediate, �: ;;
<br />t� vicinity af the storage location wliich contains the '`7 .;�,:
<br />� current instruction. In relat�ve addressing forvVat'd :, `'�
<br />°
<br />Z Register (12 bits); p�rforms s�veral functions. One, '
<br />, _ (f), the;E portion is added`to the current �cpntents :� �
<br />, it serves as a buffer register for storage. In this of the prograrn control regist�r P. \ Thus,;. the :, '��
<br />�`' capacity,. it receives the word read out of storage aperand or jump address is one .of the 63 stqrage ' 4 y��
<br />�� � � �
<br />w E� and holds the Word to, be wrrtten into storage. locations immediately preceding the `address af �' ` r'""�
<br />�}',, ; , , . ` . Also, ' for addition ' arid subtractian � erations; '"
<br />P the current instruction: An Except�on ; is .the In ;,��
<br />''� `� the _ coritents of the . Z register are added ta or direct Jum '
<br />4yiy'
<br />'� P(�, in which the jump address �s re$d
<br />;,, ' subtracted from the contents of A. ` A
<br />from the address found when the'contents af. P are ,�, y�:
<br />� added to E:
<br />,, ;
<br />� .,.t '�., . . . , ..:{ '' 1 a!r
<br />� . . . -, t �,;
<br />� P Register (12 `bits): program control register, �ts �s�
<br />, ' T�;
<br />�� t�,� contents are the address of the current instruction. ' ��e_ na address mode (n), constants are stored ,: i�;
<br />i�� _: At the begi�ning of each instruction, t�ie contents in : the address portion of `the inst�uction. The � t�
<br /><<, of P are increased by one to provide t�e address Pa�on of the instruction is not�used as an ai�diess � }:
<br />, of the :insiruction; a jump address is entered in :P Instead, it is used as a 6-bit'operand: This operand ����
<br />� if a jump is called far. �s automatically extended to 12 bits, , with �� tTae ';'�;
<br />'' u p p e r s ix b i t s; b eing zeros. Wi t h � t t iis �ea�ure , ��
<br />, ." , . ,
<br />� ���.
<br />arithmetic and; logical ope�at�ons can be cariied � t`��
<br />,; B. Register (12 bitsj : aw�iliary arithmetic register. The out with ; a 6=bit uanti ��
<br />,_ ' q ty contained m the instn�c � f:
<br />results :.of arithmetic operations are first formed tion. Thus the need ' fvr entering `man y;;coastants `° �'��
<br />,'. i n B, - t h e n i r a n s m i t t e d t o t he A, Z, or S registers. into memory is eliminated. �'�} a�
<br />,,
<br />, �: �,,
<br />, ,, , �,s �s,t
<br />'; r.; � � � � � � � �� �?,�
<br />� sti r, r�
<br />f r � . i '.. .r
<br />.. . . . . � . . . I �: l 1` ��,
<br />} { �� . � . � � . � � � . ''''''}}}
<br />,, f }
<br />�-`'
<br />'I t '," t . . . . .. . ... .. . . . . . " . . . �... � � ,
<br />Y�
<br />�,J . . . . . 1 t'��
<br />1 i �t ` � � � . � . � . . � 1 � ri
<br />x }��
<br />�� + ��t � .� . � ' � � f> �N
<br />gf'Na �rt r :' . ' . � . { � i -�bW'dI
<br />U F z��'j �.�5 , � t ;� Q t� 1�'�.�i �F
<br />1� �� :� k � t � � v� �5}�'
<br />)p��(��,s'����. i'� t^�� �:�r� { E� j � � �� i ���� v t . - i �. ',. µy.
<br />� K� il
<br />4S'"N!�il���.�� �, ir,, r`, �� � .�.F. �.nS h. l`, i t. .,. , t4JA,�:,. .. , _ �. .. � . „ . r � . . . . . x_ � � r . �. �. ;�� f' (. .. � { � Y5 y �kv ;�f'y�`
<br />_ f �k.i.. a . I , tV._�'. . .. J . . � . .. : , . . _ ., n_ . . . � . X._1Y�'�AT
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